FinFET FreePDK15 Tutorial
This tutorial is developed from ECE7332 Advanced VLSI and is created by Xinfei Guo (xg2dt) and Qin Qing (qq3za). Also Mr. Andy Whetzel contributed a lot to this tutorial.
The FinFET FreePDK15 process design kit is a 16/20nm FinFET process developed by NCSU PDK group. Nangate developed the Open Cell library. For details, please refer to the main PDK website here and here. This tutorial shows the setup, schematic capture, simulation, layout, DRC in UVa IC design environment. This tutorial assumes you have done the cadence tutorial sets that are available here.
Set up FinFET FreePDK15 in Cadence Environment at UVa
After logging in to one of the Linux machines, create your own directory for finfet PDK setup under your cadence directory. For example /cadence/finfetPDK.
The FinFET PDK is located in /app3/lib/ncsu/FreePDK15/. Please copy all the files in /app3/lib/ncsu/FreePDK15/cdslib/setup to your local folder. Please also check if cds.lib is copied successfully.
In this step, you need to create/modify setup files as you did in setting up any pdk. There are four files in total.
1.cadence-mmsim, this file is similar to other pdk. It is attached here .
2.setup.csh, this file is included in the original pdk folder copied last step. But you need to make few modifications, here  a modified version is attached, you can directly copy and paste the whole thing.
3.icoa_setup.csh, please copy from here .
4.setup-cadence, please copy from here 
Make sure you use exactly the same file name and suffix as above.
Type the following lines and hit enter after each one. Make sure to write them exactly as below, including the periods in the first two lines:
. cadence-mmsim . calibre-setup tcsh source setup-cadence virtuoso &
Your cadence window should open as following when you run 'virtuoso'. Now you finish the pdk setup!
Notice: There are only layout available right now for this finfet PDK. Also there is no model included in pdk. To run simulations, you need to create your own symbols and use PTM models. This will be covered in the following section.
Stream in NanGate Cell in Cadence Environment
NanGate developed this standard library for open use based on the FreePDK15 educational (non-manufacturable) process. Currently, the library also includes only layouts. But you could use symbols from other pdks. This tutorial will show you how to stream in NanGate library to your library manager.
Create an empty library in your library manager. For example NANGATE_CELL. A new window will pop up titled "Attach Library to Technology Library". Select the library named "NCSU_TechLib_FreePDK15" and click "OK". Now your library is properly created.
In the Stream File cell, click the browse button to the right and navigate to the file named "NanGate_15nm_OCL.gds". The absolute path is /app3/lib/ncsu/NanGate_15nm_OCL_v0.1_2014_06.A/back_end/gds/NanGate_15nm_OCL.gds.
In the Library cell, select the library you just created from the drop-down menu.
In the Attach Technology Library cell, select "NCSU_TechLib_FreePDK15" from the drop-down menu (this step may be redundant).
Click the "Show Options" button to expand the options at the bottom of the Window. Click on the tab labeled "Layers". Under the area at the bottom left called "Map File", click the "Load" button.
The layermap is located in /app3/lib/ncsu/FreePDK15/cdslib/NCSU_TechLib_FreePDK15/NCSU_TechLib_FreePDK15.layermap
Finally, click Translate. It may take up to a minute to stream in completely. Once it is done you will get a message telling you how many errors and warnings there were in the translation. Errors are fatal, but warnings can often be benign.
The library is shown in your library manager now.
Now you can open the layout. Here is an example of inverter.
Use FreePDK15 with Cadence
Right now, the pdk could be mostly helpful for physical design. You can run DRC as regular pdk, but lvs is not available due to they haven't provided the rules file.
The following are some related documents provided by NCSU.
Current Design Rules
Design Rule Manual
Simulate FinFET PTM model with HSPICE
The PTM Finfet model is available to download at Here. After downloading the .zip file, please unzip it to your local directory. The folder includes all the models across 4 different technology. Here I show an example of simulating an inverter with 7nm finfet model. The netlist (inverter.sp) is shown in the following.
* Basic Inverter with finfet *.lib '/net/plato.ee.Virginia.EDU/users/xg2dt/HSpice/finfet/models' ptm20lstp .include '7nfet.pm' .include '7pfet.pm' .PARAM .OPTION POST .GLOBAL gnd! vdd! .SUBCKT inv vi vo MM1 vo vi gnd! gnd! nfet nfin=1 MM0 vo vi vdd! vdd! pfet nfin=1 .ENDS XINV A Y INV C0 Y gnd! 2E-15F Vvdd vdd! 0 0.7v Vgnd gnd! 0 0v *VIN A 0 VIN A 0 0 pulse 0 0.7 0 50p 50p 2n 4n *DC VIN 0 1.8 0.01 .tran 10p 10n .END
Run HSPICE by typing
hspice -i inverter.sp
To view the waveform of the simulation, type
wv inverter.tr0 &
Simulate FinFET PTM model with Spectre
The latest finfet PTM not only supports SPICE simulation, it also has the SPECTRE flavor. This part of the tutorial will show the simulation setup with SPECTRE. One way to simulate with spectre is to write the netlist manually without using symbold, but it doesn't work well with large circuit. So creating a symbol that could be instantiated in design is preferred.
Step 1: Create the symbol for pfet/nfet
Since there are no symbols included in the PDK. But we can simply use the same symbols from other PDK (FreePDK45nm) with little modifications. The following shows the steps.
- Add the device library of FreePDK45nm to your library. The path is /app/lib/freepdk45/trunk/ncsu_basekit/lib/NCSU_Devices_FreePDK45 and /app/lib/freepdk45/trunk/ncsu_basekit/lib/NCSU_TechLib_FreePDK45
- Create a new library where you will create your finfet devices symbols in, or you can add the symbols into NCSU_TechLib_FreePDK15 library. In this example, I created a seperate library called FinFET_Sim.
- Copy pfet and nfet symbol from NCSU_Devices_FreePDK45 to the library you just created. The device name can be defined by yourself. To keep consistent, I named them pmos_vtl and nmos_vtl.
- To modify/define the cdf parameter of the symbol, go to virtuoso>Tools>CDF>Edit.
- Edit the parameter or remove some parameters that are not neccessary for this finfet model. For examples parasitics cap and length are already included in the models. In this demo, I keep the multiplier tab for sizing the transistor. Increase the value of this multiplier will upsize the transister, and vice versa. Note for finfet, you can only size it by increasing # of fingers, which means you can only have 2X, 3X... and you can't have 1.5X. That is a limitation of finfet, and this is called Width Quantization.
- After modification, the symbol is ready to use!
Step 2: Design the Finfet based circuit
Now you can create the design by using the finfet symbols by pressing "i" in schematic. Here I show an example of inverter. Notice that the body terminal can be connected to any node or left floating.
Also to make sure the symbol can be recognized by the model, you need to modify the Model Name part in device property (Press "P"). For PMOS, the Model Name is pfet, and NMOS is nfet.
Step 3: Download the models
The PTM Finfet model is available to download at Here. After downloading the .zip file, please unzip it to your local directory. There are 3 parts in the folder. modelfilesfolder includes all the .pm models for different technologies. modelfile is an entry file that includes all the paths of the .pm model. We only need to include this file during our simulation.Notice that this model file uses the .pm model from last folder level, so you could either modify the path by removing ".." or copy modelfiles and param.inc to the last level of the folder, please be aware of this. param.inc includes all the parameters used in the model, including vdd
Step 4: Simulate with Spectre
Open ADE L in cadence, in Model Library section, choose model file mentioned in Step 3. Notice you could choose the technology node and the sub-model from section part. The rest of the process is exactly the same as other PDKs. Please refer to the FreePDK45nm tutorial for details.
- If you want to write your own spectre netlist, the format of the library path is include "library path/models" section=ptm16hp.
- 2015 Spring ECE7332 - Stack Height Analysis for FinFET Logic and Circuit by Xinfei Guo and Qin Qing
- 2015 Fall ECE6332 - A Comparison of FET Devices: FinFETs vs. Traditional CMOS by Walive Pathiranage Manula Randhika Pathirana, Matthew Ridder and Luis Lopez Ruiz